Integrated circuits (IC's) are prone to damage and failure from an electro-static-discharge (ESD) pulse. ESD failures may occur in the factory and contribute to lower yields. ESD failures may also occur in the field when an end-user touches a device. Smaller devices such as security chips in a smart credit-card or bank card are especially prone to ESD failure. As credit cards are replaced with smart cards using Integrated Circuit (IC) chips, many ESD failures will occur using the present ESD technology.
Various ESD-protection structures have been placed near input, output, or bi-directional I/O pins of ICs. Many of these protection structures use passive components such as series resistors, diodes, and thick-oxide transistors. Other ESD structures use an active transistor to safely shunt ESD current.
As manufacturing ability improves and device sizes shrink, lower voltages are applied to transistors during normal operation. These smaller transistors are much more susceptible to over-voltage failure but can operate with a lower power-supply voltage, thus consuming less power and producing less heat.
Such smaller transistors are often placed in an internal “core” of an IC, while larger transistors with gate lengths that are above the minimum are placed around the core in the periphery. ESD-protection structures are placed in the periphery using these larger transistors.
Thinner gate oxides of the core transistors can be shorted, and substrate junctions melted by relatively small capacitivly-coupled currents applied to the tiny core devices. Static charges from a person or machinery can produce such damaging currents that are only partially blocked by the input-protection circuits in the periphery.
FIG. 1 shows a chip with several ESD-protection clamps. Low-voltage core circuitry 20 contains core transistors 22, 24, which have a small channel length and can be damaged by currents at relatively low voltages. Low-voltage core circuitry 20 receives a power supply voltage VDD, such as 1.8 volts, 1.2 volts, or some other value. There may be thousands of core transistors in low-voltage core circuitry 20.
Protection from ESD pulses may be provided on each I/O pad, and by power clamp 26. Power clamp 26 is coupled between VDD and ground (VSS), and shunts current from an ESD pulse between the power rails.
Some cross-coupling may occur between different pads and low-voltage core circuitry 20, such as through substrates and capacitances. An ESD pulse applied to one I/O pad 10 may be coupled into low-voltage core circuitry 20 by this cross-coupling, causing damage to transistors 22, 24 in low-voltage core circuitry 20. Power clamp 26 may shunt enough current from the ESD pulse to reduce such cross-coupling to prevent damage. ESD pulses applied to I/O pins may still couple into low-voltage core circuitry 20, such as through power lines, but power clamp 26 may then be activated to reduce potential damage. Power clamp 26 may also turn on for other ESD pulses such as those applied to I/O pins, when the ESD pulse is shunted through a diode in the I/O pin's ESD-protection structure to the internal VDD rail, causing an indirect VDD-to-VSS ESD pulse. For example, an ESD pulse applied to I/O pad 10 may cause ESD protection device 12 to turn on to conduct to VDD.
Each I/O pad 10 may be outfitted with several ESD protection devices 12, 16 to protect against various possibilities. ESD protection device 16 turns on for a positive ESD pulse applied from ground to I/O pad 10, while ESD protection device 18 turns on for a positive ESD pulse applied from ground to I/O pad 10. Likewise, ESD protection device 12 turns on for a positive ESD pulse applied from I/O pad 10 to VDD while ESD protection device 14 turns on for a positive ESD pulse applied from I/O pad 11 to VDD. Power clamp 26 may also turn on in some situations.
Some prior-art ESD protection structures have large-area capacitors, resistors, or transistors which are undesirable. Some prior-art ESD-protection devices are not suited to standard CMOS processes, such as ESD-protection devices that use insulator layers in Silicon-On-Insulator (SOI) processes. Diodes have been uses as ESD-protection structures, but the diode's I-V characteristics allow for high voltages when large ESD currents flow, and these high voltages can still damage core transistors. Some ESD-protection structures use two diodes in series rather than one diode, but such stacked diodes are undesirable in some environments due to the increased voltage drop of two diodes in series. Silicon-Controlled Rectifiers (SCR's) have also been used successfully. Both an SCR and a diode may be used. However, simply having a diode and an SCR in an ESD-protection structure may produce erratic results that depend on the relative locations of the SCR and diode and other structures such as guard rings.
What is desired is an electro-static-discharge (ESD) protection circuit with both a diode and a SCR. An ESD protection device featuring parallel diode and vertical SCR paths to allow for better optimization is desirable. Tightly integrating a diode and an SCR is desired.